(1) Field of the Invention
The present invention relates to the manufacture of semiconductor devices, and in particular, to a method of forming a modified nitride spacer for solving charge retention problem in a floating gate memory cell.
(2) Description of the Related Art
Spacers are used for several different purposes in the manufacture of semiconductor devices, among them for structural as well as electrical and programmability reasons. A well-known structural use, shown in FIGS. 1a-1f, is in the manufacture of field effect transistors (FETs), which are also very well-known for their very small size, high packing density in the Ultra Scale Integration (ULSI) technology. Employing conventional methods, gate-oxide layer (30) is first formed over substrate (10) having already defined active regions bounded by passive field oxide regions (20) shown in FIG. 1a. A polysilicon layer is blanket deposited over the substrate and etched to form poly-gate (40), as shown in FIG. 1b. Gate-oxide other than that underlying the poly-gate is also etched away. Using poly-gate as a self-aligned mask, ion implantation is usually employed to form source and drain regions (15). Subsequently, an oxide layer (not shown) is formed over the substrate and anisotropically etched, following conventional methods, to form oxide spacers (50) shown in FIG. 1c. 
One of the early structural uses of oxide spacers such as shown (50) in FIG. 1d was in forming self-aligned silicide (SAC) contacts, which are well-known in the art. Thus, after the forming of the spacers, metal used to form the silicide is deposited over the substrate. The substrate is then heated, which causes the silicide reaction to occur wherever the metal is in contact with the silicon. Everywhere else, the metal remains unreacted. The unreacted metal is selectively removed through the use of an etchant that does not attack the silicide, the silicon, or the oxide. As a result, each exposed source and drain region is now completely covered by silicide film (60), out there is no film elsewhere. A dielectric layer, (70), is next deposited onto the silicide, and contact holes are opened in it down to the silicide layer following conventional techniques (FIG. 1e). Metal (80) is deposited into the contact holes to make contact with the silicide, which provides excellent electrical characteristics. Thus, the oxide spacers have performed the structural function of separating silicided areas from shorting each other, and also, as it will be known to those skilled in the art, providing tapered holes for making good tapered self-aligned silicide (SAC) contacts.
However, spacers (50) on the sidewall of gates, hence sometimes called sidewall spacers, also provide an important function in aligning ion implants which in turn control electron flow to and fro between the floating gate and the channel in the semiconductor substrate. In FIG. 1f, which is redrawn from FIG. 1d, the length of the space bounded by the source/drain regions (15) under poly-gate (400) is defined as the channel length (13) of the FET. As the advances in ultra scale integration continues, the channel length is further reduced resulting in undesirable short channel effects (SCE). This is due to the fact, as it will be known to those skilled in the art, that the band gap and built-in potential at junctions are an intrinsic property (constant) of the crystalline materials (such as silicon), and are non-scalable with the further reduction in device dimensions. One of the SCE effects exhibits itself, what is known as the hot carrier effect (HCE). This is where electrons ejected from the drain area can acquire sufficient energy to be injected into the gate oxide resulting in charge buildup in the oxide that causes threshold voltage shifts. Unfortunately, HCE is known to severely degrade the performance of FET devices.
One common method of minimizing these short channel effects is to fabricate FET structures with Lightly Doped Drains (LDDs), actually, including the source regions also. These LDD structures are formed using sidewall spacers, such as shown in FIG. 1f, and two implants. The LDDs serve to absorb some of the potential into the source/drain (S/D) regions and thus reduce the maximum electric field. One of these implants is self-aligned to the gate electrode, and forms lightly doped S/D regions (15) shown in FIG. 1f. The purpose of the first implant dose is to produce lightly doped section of the drain at the gate edge near channel (13). The heavier second implant is self-aligned to spacers (50), and forms a low resistivity region (17) of the S/D regions, which are also merged with the previously formed lightly doped regions (15), as seen in FIG. 1f. Since the heavily doped regions (17) are further away from the channel than would be the case in a conventional structure without the LDD, the depth of the heavily doped region can be made somewhat greater without adversely impacting the device operation. The increased junction depth lowers both the sheet resistance and the contact resistance of source/drain regions.
In prior art, sidewall spacers are also used to form the lightly doped S/Ds, or LDDs, by solid-phase diffusion from a doped oxide source that is also used as the sidewall spacers. Thus, doped side-wall spacers are formed by depositing a doped oxide (e.g., phosphosilicate glass (PSG)) and anisotropically etching as shown in FIG. 1f. After implanting the source/drain contact areas (17) (N+), the substrate is annealed to drive in the dopant to form the lightly doped source/drain areas (15) (Nxe2x88x92) and to activate and anneal out the implant damage in the N+ source/drain areas. However, the LDD regions (15) now extend further under the poly-gate, or gate electrode (40) such that the effective length of channel (13) is considerably reduced, sometimes by about one-half the original length of the channel. Thus, for an FET with a 0.2 xcexcm gate width, the effective channel length could be only about 0.1 xcexcm. In other words, gate electrode (40) significantly overlays the out diffused lightly doped S/D regions (15) resulting in high gate-to-drain capacitance that degrades the RC delay time, as it will be known to those skilled in the art. Also, the LDD S/D regions extending significantly under the gate electrode results in unwanted short channel effects, such as hot carrier injection in the gate oxide.
Huang of U.S. Pat. No. 5,989,966 proposes a method for suppressing such short channel effects by forming gate oxide on a substrate and patterning a polysilicon to form a gate electrode; forming first spacers comprising silicon nitride on the sidewalls of the gate electrode; forming second sidewall spacers from a doped oxide that serve as a solid-phase diffusion source; implanting S/D regions adjacent second sidewall spacers; annealing the substrate to diffuse dopant from the second sidewall spacers to form the lightly doped S/D regions; thus using the first silicon nitride spacers to serve as a diffusion barrier so that the LDDs formed under the gate electrode do not intrude as much into the channel area under the gate electrode. And hence, the reduced gate-to-drain overlay capacitance and improved immunity to hot electron effects.
Another method for achieving increased resistance to hot carrier damage with the use of sidewall spacers is disclosed by Aminzadeh, et al., in U.S. Pat. No. 5,827,769. Here, an oxide is grown on the gate electrode. This oxide s strengthened by nitridation and anneal. After a light doped drain implant, a second side oxide and a conformal nitride layer are deposited. Then, the conformal nitride is anisotropically etched to form spacers for masking a high dose drain implant. An NMOS transistor fabricated with this process has been found to be forty percent less susceptible to hot carrier damage than a conventional LDD process.
In another U.S. Pat. No. 5,966,606, a sidewall spacer formed through nitridation of the gate electrode is disclosed by Ono. A sidewall film of a gate electrode is first fabricated as a two-layer structure including an underlying thin silicon nitride film and a relatively thick silicon oxide film. The silicon nitride film covers and protects the edge of the gate oxide film against formation of a gate bird""s beak at the edge of the gate oxide film. The sidewall film spacer contacts with the silicon substrate substantially at the thick silicon oxide film of the sidewall, which prevents formation of a carrier trap area adjacent the channel area.
Keller, et al., show in U.S. Pat. No. 5,985,719, multi sidewall spacers in a method of forming a programmable non-volatile memory cell. A non-oxide spacer is formed over the sidewall of a gate electrode, covered by a shielding spacer, which may comprise silicon nitride, oxynitride compounds or aluminum, and again followed by another dielectric layer on the shielding layer. In still another U.S. Pat. No. 5,573,965, Chen, et al., use sidewall spacer technology to fabricate semiconductor devices and integrate circuits. The spacers are formed as composite, multi-layered structures of silicon oxides or of silicon oxides and silicon nitride. On the other hand, Hasegawa of U.S. Pat. No. 5,460,992 shows fabricating a non-volatile memory device with a multi-layered gate electrode structure by forming a floating gate electrode and a thermally oxidized silicon film on surfaces inclusive of a surface of the multi-layered gate electrode structure having a control gate, and then forming, by a thermal nitrifying treatment, a thermally nitrified oxidized silicon film at an interface between the thermally oxidized silicon film and the multi-layered gate electrode structure.
In a different U.S. Pat. No. 5,915,178, Chiang, et al. , teach a method for improving the endurance of split gate flash EEPROM devices via the addition of a shallow source side implanted region.
Prior art shows the use of sidewall spacers for various purposes. It is shown in the present invention that by a judicious choice of materials in a particular sequence of sidewall spacers of certain widths, charge retention in non-volatile, floating gate memories can be improved substantially.
It is therefore an object of this invention to provide a method of forming a modified nitride spacer to improve charge retention in floating gate memory cells.
It is another object of this invention to provide method of forming a modified nitride spacer with a layer of oxide formed between the sidewalls of a floating gate electrode and the nitride spacer, and in that order only, in order to increase resistance to charge movement between the floating gate and the modified nitride spacer.
It is still another object of this invention to provide method of forming a pure oxide spacer to improve charge retention in floating gate memory cells.
It is yet another object of the present invention to provide a modified nitride spacer and a pure oxide spacer to improve charge retention in floating gate memory cells.
These objects are accomplished by providing a semiconductor substrate doped with a first conductive type dopant and having a plurality of active and field regions defined; forming a gate oxide layer over said substrate; forming a polysilicon layer doped with a second conductive type of dopant over said gate oxide layer; patterning said polysilicon layer to form a gate electrode having sidewalls over said gate oxide layer; performing first ion implant on said substrate using said gate electrode as a mask to form lightly doped source/drain regions; forming an oxide layer over said gate electrode; forming a nitride layer over said oxide layer; etching anisotropically said silicon nitride layer to form nitride spacers on sidewalls of said gate electrode; and performing second ion implant on said substrate using said nitride spacers as a mask to complete the forming of sad source/drain regions.
These objects are also accomplished in a second embodiment where only pure oxide is used in making spacers on the sidewalls of the floating gate in order to improve the charge retention characteristics of the floating gate memory cell.
The objects of the instant invention are further accomplished by providing a modified nitride spacer and a pure oxide spacer to improve charge retention in floating gate memory cells.